Dennis Agyemanh Nana Gookyi, Kwangki Ryoo, Vol. 3, No. 1, pp. 11-20, Mar. 2021
10.22662/IJASC.2021.3.1.011, Full Text:
Keywords: NIST, Lightweight cryptography, AEAD, SpoC, FPGA

Abstract

Background/Objectives: This paper presents the hardware implementation of SpoC Lightweight Cryptography (LWC) candidate for low-cost devices. Methods/Statistical analysis: The proposed hardware implementation of the SpoC Authenticated Encryption with Associated Data (AEAD) is capable of both encryption and decryption. The design was implemented on the Virtex-4 Field FPGA using Xilinx ISE Design Suite. The synthesis results reported 951 slices at 246.61 MHz maximum clock frequency. The encryption and decryption routines take 589 and 590 cycles. Findings: This work used 30% fewer LUTs for both encryption and decryption as compared to the existing work. The decrease in area in this work is a result of the optimization of the implementation for low-cost devices while the existing work implemented the basic iterative architecture without optimizing. This work achieved almost two times the frequency of the existing SpoC implementation. The existing SpoC implementation used 150 fewer cycles as compared to this work. This is because this work implemented the SpoC using extra registers in other to reduce the critical path which increases the frequency. Improvements/Applications: For future works, the proposed SpoC AEAD will be combined with other security protocols to form a lightweight cryptographic System-on-Chip (SoC).

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